FIG. 1 is a block diagram of a dimmable light ballast system 10. The system 10 includes a microcontroller 12 which typically controls a dimmable light ballast 16 via its controller 11 and a timer structure 14. Electronic dimmable ballasts are controlled by on/off pulses. Varying the pulse lengths up and down controls the brightness of the light. A pulse is typically generated by dividing a frequency base through a series of fixed prescalers and/or programmable dividers. High resolution frequency control in dimmable light ballasts is conventionally addressed by using a low frequency digital part which is connected to analog components. This combination of elements converts low frequency pulses to a series of high frequency pulses. This method is referred to as indirect PWM control.
Light ballasts are utilized in a variety of applications. Oftentimes, these light ballasts are dimmable. However, it is important that the dimming resolution be of high resolution to allow for a variety of settings of light.
The resolution for a traditional timer frequency divider is:
                              f          GEN                =                              f            BASE                    n                                    (        1        )            
The human eye is sensitive to variations of the light level, and frequency changes must be small for the eye not to notice. The frequency can be changed with a resolution expressed by equation 2 below.
                              Δ          ⁢                                          ⁢                      f            GEN                          =                                                            f                BASE                                            n                -                1                                      -                                          f                BASE                            n                                =                                    f              BASE                                      n              *                              (                                  n                  -                  1                                )                                                                        (        2        )            
For a high resolution light ballast, the target for frequency change is less than 50 Hz. At 80 kHz frequency and 50 Hz resolution the divider value becomes:
                              Δ          ⁢                                          ⁢                      f            GEN                          ≤                                            f              GEN                        *            n                                n            *                          (                              n                -                1                            )                                                          (        3        )            
Solving equation (3) for a frequency of 80 kHz and a resolution of 50 Hz gives n=1600. Inserting n=1600 gives a frequency base of 80 Hz*1600=128 MHz which is a very high frequency.
Today designs are using lower frequency timer outputs, which are multiplied externally to higher frequencies, often using analog technology, i.e., an indirect method is used to control the pulse width. These designs therefore are controlled by some type of timer structure. There are a variety of known timer structures. Some of them are described in summary fashion below.
1. Advanced Timer Structures
Advanced timer structures have previously been used in microcontrollers to allow use of multiple frequencies. Some typical methods include:
a. Timer with Down-counter and Reload Registers
The counter counts down until it reaches zero. It then reloads from a reload register, toggles an output and interrupt a processor, which can load the reload register with a different value. For 50% duty cycle, a single register per pulse is needed. If pulse width modulation is needed, two reload registers per pulse are needed. Very few processors support interrupt rates at the frequencies used in ballasts. This type of timer is very common, both in low and high-end controllers.
b. Timer with Down-counter and Multiple Reload Registers
A variation of the counter above uses multiple reload registers. Typically an additional set is used. The use of this structure is mainly to allow a frequency to change as a result of an external event, and will only allow a single change, without processor intervention.
Again, this results in very high interrupt rates. An additional counter can be connected allowing the frequency to change only after a number of pulses has been generated.
c. Timer Complex with Chain Mode
To achieve the average frequency improvement to 1/16th of that of a single frequency, 16 or 32 reload registers are needed. Such implementations are available in advanced processors. The timer complex may have a “chain” mode, where a timer controls an output on the microcontroller. It operates for a certain time, but when a specific event occurs, it will forward control of output to a different timer which is “chained” to the first timer. The Motorola TPU Timer Processing Unit is a typical example of such a timer. The TPU is implemented using a programmable controller and uses significant chip area.
d. Timer with Down-counter and Reload Registers and DMA Support
Some processors can maintain the reload registers in a table in an inexpensive SRAM. When the counter is loaded from the reload register, a DMA request is generated, and the DMA controller will load the reload register from the table. The DMA can support a circular buffer structure where the index of the table is automatically reset to the start of table when the end of table is reached. While this implementation is less expensive than the timer complex, it is still fairly expensive, and is not good for low cost implementation. This implementation is typically used for motor control.
e. Serial Interfaces
Serial communications peripherals with bit rates at the base frequency can be used to generate any bit sequence, and can obviously be used to emulate a timer. This relies on storing the bit pattern in an internal buffer and is much more expensive than the timer structure, making it unattractive for low cost implementation.
f. Timer with Up/Down-counter and Compare Registers
A timer structure similar to the down counter with reload is the counter with compare register. The timer counts up/down until a programmable value is reached. It then either reloads with a fixed value or from a small set of fixed values, or changes direction. Both structures are inherently relying on large blocks of external hardware in the form of processors, multiple reload registers or DMA support to change the frequency.
g. PWM Timer with Dithering Support
Some low-end microcontrollers implement Digital to Analog converters using a pulse width modulated timer. The output is filtered through an analog filter, and the output voltage is depending on the pulse width of the timer (ratio tHIGH/(tHIGH+tLOW). By varying the pulse width, the output voltage can be changed. The cost of the analog filter is depending on the PWM frequency and it is desirable to avoid lower frequencies. The problem is similar to that of the ballast, since dividing a base frequency with a programmable value generates the PWM frequency.
To increase the resolution of the D/A converter, some microcontrollers (including those focusing on CRT monitors) use dithering or flank width modulation. The PWM pulses are divided into frames of longer or shorter than the nominal value in a pulse width register. The “average” pulse length is thus increased or decreased by 1/nth of a clock pulse every time a flank is modulated. The PWM frequency is not changed to avoid problems with the analog filter.
h. Clock Generator with Added Noise
Some clock generators used to provide a system clock for an electronic system vary the frequency over a short frequency interval to divide the energy over a larger frequency spectrum. This function is mainly there to reduce EMI, and chips implementing this normally does not allow controlling the variation of the clock frequency in a predictable manner, and generally lack all other features necessary to implement ballast control.
Accordingly, all of the above implementations either require complex circuitry and typically require microcontrol. The present invention addresses such a need.